Multi-Chip Package

Product Overview

ASE's MCP(Multi-Chip Package) employs thin core substrate and wafer thinning technology so as to provide multi-die structures for increased device functionality while maintaining size reduction. It provides efficient use of motherboard and allows for size and weight reduction as well as cost reduction needs of system level.

Application

Multi-chip package provides an integrated packaging solution for products requiring increased memory density and performance such as cell phone, PDA, wireless LAN, digital camera and system module.

• Memory + Memory
• Logic + Memory
• ASIC + Memory
• DSP + Memory
• SiP

Features

• Thinner profile with dies stacking platform
• Compatible with standard FBGA infrastructures and footprints
• Thinner spacer technology
• Wire bonding on die overhang
• Wafer thinning and handling to 75um
  

Reliability

• Moisture sensitivity level: JEDEC Level 3 @260°C
• Temperature cycling: -65°C / +150°C (condition'C'), 1000cycles
• Autoclave: 121°C/100%RH/2atm, 168 hours
• High temp storage: 150°C, 1000 hours
• HAST (unbiased): 130°C/85% RH/2atm, 96 hours
• Temperature/Humidity test: 85°C/85°C RH, 1000 hours

Standard material

• Package substrate
  -Layer: 2~4 layer
  -Laminate: Laminate (BT or equivalent)
• Die attach adhesive:
  - Bottom: Silver filled or non-conductive epoxy
  - Top: Non-conductive or film adhesive
• Encapsulant: Low stress epoxy material
• Solder ball: 63Sn/37Pb(Eutectic), Sn/3~4Ag/0.5Cu(Lead free)
• Marking: Laser

Shipping

Tape and reel or trays